An effective low powr design methodology based on interconnect prediction

• Authors: Shih-Hsu Huang
• Venue: Proceedings of the 2001 international workshop on System-level interconnect prediction
• Year: 2001

The demand for low power digital systems has motivated significant research. However, the power estimation at the logic level is a difficult task because interconnect plays a role in determining the total chip power dissipation. As a result, the power optimization at the logic level may be inaccurate due to the lack of physical place and route information. In this paper, we will present an effective low power design methodology based on interconnect prediction at the logic level. The proposed design methodology includes the method to create wire load models and the design procedures to select the appropriate wire load model during synthesis. The main distinction of the proposed approach is that it constructs physical hierarchy during the synthesis stage. By taking advantage of wire load models, the proposed design methodology is able to develop low power digital systems while speeding up the design process. Experimental data shows that this design methodology achieved very good results.