Switching response modeling of the CMOS inverter for sub-micron devices

Authors:
L. Bisdounis;S. Nikolaidis;O. Koufopavlou;C. E. Goutis
Affiliations:
VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece;Electronics & Computers Division, Department of Physics, Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece;VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece;VLSI Design Laboratory, Department of Electrical & Computer Engineering, University of Patras, 26500 Patras, Greece
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 2
Cited 0

Principles of CMOS VLSI design: a systems perspective

Principles of CMOS VLSI design: a systems perspective
Methods to improve digital MOS macromodel accuracy

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper an accurate, analytical model for the evaluation of the CMOS inverter delay in the sub- micron regime, is presented. A detailed analysis of the inverter operation is provided which results to accurate expressions describing the output waveform. These analytical expressions are valid for all the inverter operation regions and input waveform slopes. They take into account the influences of the short- circuit current during switching, and the gate-to- drain coupling capacitance. The presented model shows clearly the influence of the inverter design characteristics, the load capacitance, and the slope of the input waveform driving the inverter on the propagation delay. The results are in excellent agreement with SPICE simulations.