Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Minimizing energy dissipation in high-speed multipliers
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
0.6V correlators for WLAN receivers
SARNOFF'09 Proceedings of the 32nd international conference on Sarnoff symposium
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A low-power design circuit using low-swing voltage technique is proposed in this paper. The proposed technique could be used in order to decrease the power dissipation in three different types of logic gates namely the complementary pass-transistor logic (CPL), the cascade voltage switch logic (CVSL), and the domino logic. The main idea of the proposed technique is based on the replacement of the conventional CMOS inverter at the output of the logic gates with a new low-swing voltage inverter based on multithreshold voltage technology (LSIM). The inserted LSIM achieves a reduction in the static power dissipation, the dynamic power dissipation as the propagation delay time of the gates. To demonstrate the impact of the proposed technique in different applications, various types of circuits are designed for different conditions of: speed operation, load capacitance and supply voltages. In order to ensure the validity of the proposed technique in large circuit designs and fanout, a 8_bit Braun multiplier is designed in the three types of logic gates. SPICE simulation results for 3.3 V supply voltage using 0.5 µm multithreshold technology prove that 32%, 30% and 34%, reduction in power dissipation and 10%, 12% and 15% reduction in delay time could be achieved for the CPL, CVSL and domino logic gates respectively.