Comments on 'Ternary Scan Design for VLSI Testability' by M. Hu and K.C. Smith

  • Authors:
  • R. F. Molyneaux;A. Albicki

  • Affiliations:
  • Univ. of Rochester, Rochester, NY;Univ. of rochester, Rochester, NY

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 1989

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Abstract

An alternative design is found to be significantly faster than the one proposed by Hu and Smith. The performance of the alternative is compared to the original. A means to buffer the signal is presented and its performance is reported. An estimate of silicon area saved versus area spent is made.