Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations

  • Authors:

  • Tassos Markas;D. Mark Royals;Nick Kanopoulos

  • Affiliations:

  • Center for Digital Systems Engineering, Research Triangle Institute, Research Triangle Park, NC;Bell-Northern Reasearch/Northern Telecom, Research Triangle Park, NC;Center for Digital Systems Engineering, Research Triangle Institute, Research Triangle Park, NC

  • Venue:
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Year:
  • 1994

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Abstract

In this paper, we present the design and implementation of a bus-monitor unit targeted for the design of highly reliable fault-tolerant systems. The bus-monitor is designed using Differential Cascode Voltage Switch (DCVS) logic, whose inherent characteristics result in self-checking circuits. It is implemented in an Application Specific Integrated Circuit that can be used to implement a variety of fault-tolerant architectures including Triple Modular Redundant and Hybrid configurations. The unit is capable of detecting and correcting failures in the redundant modules by monitoring their respective buses, and it delivers fault-free data to the destination modules. The unit is also capable of detecting faults occurring in the unit itself by utilizing the fault secure properties of DCVS logic. In this paper, we present the operation of the bus-monitor unit and we describe its DCVS design and implementation, as well as the performance characteristics of the prototype chips. Finally, we illustrate how the bus-monitor unit(s) can be used to implement highly reliable fault-tolerant architectures, and we demonstrate that architectures designed using the developed unit(s) exhibit higher reliability compared to the ones implemented with CMOS logic, using the same number of computational resources.