Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Testing functional faults in VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Testing DSP cores based on self-test programs
Proceedings of the conference on Design, automation and test in Europe
Functional Tests for RISC-microprocessors
Automation and Remote Control
A study on the extended unique input/output sequence
Information Sciences: an International Journal
| Hi-index | 14.98 |
A method is presented for functional testing of microprocessors. First, a control fault model at the RTL (register transfer language) level is developed. Based on this model, the authors establish testing requirements for control faults. They present two test procedures to verify the write and read sequences, and use the write and read sequences to test each instruction in the microprocessor. By utilizing k-out-of-m codes, they use fewer tests to cover more faults, thereby reducing the test generation time.