Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
A roving monitoring processor for detection of control flow errors in multiple processor systems
Microprocessing and Microprogramming - Fault tolerant computing
Watchdog Processors and Structural Integrity Checking
IEEE Transactions on Computers
Software faults: A quantifiable definition
Advances in Engineering Software
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This paper presents a new approach to the on-line detection of control flow errors caused by transient and intermittent faults in microprocessor systems. It is based on the idea of signatured instruction streams. Signatures are embedded into the program memory using the monitored processor instructions. Compared with existing techniques the presented approach is universal and it can be easily implemented using off-the- -shelf PAL and LCA circuits. The hardware overhead ranges from one to several chips for microprocessors with 8-bit and 16-bit data buses. Program memory overhead is 10-20% and quite of ten no extra memory chip is required. A special software module has been developed to embed signatures and checkpoints into application programs.