Reliability modeling and architecture of ultra-reliable fault-tolerant digital computers
Reliability modeling and architecture of ultra-reliable fault-tolerant digital computers
On Reliability Modeling and Analysis of Ultrareliable Fault-Tolerant Digital Systems
IEEE Transactions on Computers
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Automatic Generation of Symbolic Reliability Functions for Processor-Memory-Switch Structures
IEEE Transactions on Computers - Lecture notes in computer science Vol. 174
A Unified Reliability Model for Fault-Tolerant Computers
IEEE Transactions on Computers
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The large number of different redundancy schemes available to the designer of fault-tolerant systems, the number of parameters pertaining to each scheme, and the large range of possible variations in each parameter seek automated procedures that would enable the designer to rapidly model, simulate and analyze preliminary designs and through man-machine symbiosis arrive at optimal and balanced fault-tolerant systems under the constraints of the prospective application.