Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique

Authors:
Gong Rui;Chen Wei;Liu Fang;Dai Kui;Wang Zhiying
Affiliations:
National University of Defense Technology, P.R. China;National University of Defense Technology, P.R. China;National University of Defense Technology, P.R. China;National University of Defense Technology, P.R. China;National University of Defense Technology, P.R. China
Venue:
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Year:
2006

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Abstract

Two modified Triple Modular Redundancy (TMR) structures based on asynchronous circuit technique are proposed in this paper. Double Modular Redundancy (DMR) structure uses asynchronous C element to output and keep the correct value of two redundant storage cells. Temporal Spatial Triple Modular Redundancy structure with DCTREG (TSTMR-D) uses explicit separated master and slave latch structure of de-synchronous pipeline. Three soft error tolerant 8051 cores with DMR, TMR and TSTMR-D respectively are implemented in SMIC 0.35ìm process. Fault injection experiments are also included. The experiment results indicate that DMR structure has a relatively low overhead on both area and latency than TMR, while tolerances SEUs in sequential logic. TSTMR-D structure can tolerance soft errors in both sequential logic and combinational logic with reasonable area and latency overhead.