Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement
IEEE Transactions on Computers
Improving cache lifetime reliability at ultra-low voltages
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
Unequal-error-protection codes in SRAMs for mobile multimedia applications
Proceedings of the International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A new class of multiple-error correcting codes has been developed. Since it belongs to the class of one-step-decodable majority codes, it can be decoded at an exceptionally high speed. This class of codes is derived from a set of mutually orthogonal Latin squares. This mutually orthogonal property provides a class of codes having a unique feature of "modularity." The parityc heck matrix possesses a uniform pattern and results in a small number of inputs to modulo 2 adders. This class of codes has m2 data bits, where m is an integer, and 2tm check bits for t-error correcting.