An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

Authors:
Marco Lanuzza;Paolo Zicari;Fabio Frustaci;Stefania Perri;Pasquale Corsonello
Affiliations:
Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Rende, Italy 87036;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Rende, Italy 87036;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Rende, Italy 87036;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Rende, Italy 87036;Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, Rende, Italy 87036
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

Citing 2
Cited 1

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Error Correction Coding: Mathematical Methods and Algorithms

Error Correction Coding: Mathematical Methods and Algorithms

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

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Abstract

This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUs). A novel configuration scrubbing core, instantiated at the top level of the user project, is used for internal detection and correction of SEU-induced configuration errors without requiring further external radiation hardened control hardware. As demonstrated in the paper, this approach combines the benefits of fast SEU faults detection with fast restoration of the device functionality and small overhead. Moreover, the proposed technique result highly versatile and can be adopted for different FPGA device families.