FPGA-Based Fault Injection for Microprocessor Systems
ATS '01 Proceedings of the 10th Asian Test Symposium
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Leakage control in FPGA routing fabric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fault Injection-based Reliability Evaluation of SoPCs
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs
ETS '07 Proceedings of the 12th IEEE European Test Symposium
On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)
FCCM '09 Proceedings of the 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines
Short-Circuits on FPGAs Caused by Partial Runtime Reconfiguration
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Fault Injection Results of Linux Operating on an FPGA Embedded Platform
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping
FCCM '11 Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
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An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the "hard core" PowerPC, running the Linux OS and several peripherals implemented in "soft" (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that the Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is mapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within the system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller.