Highly Fault-Tolerant FPGA Processor by Degrading Strategy

Authors:
Yousuke Nakamura;Kei Hiraki
Affiliations:
-;-
Venue:
PRDC '02 Proceedings of the 2002 Pacific Rim International Symposium on Dependable Computing
Year:
2002

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Abstract

The importance of highly fault-tolerant computing systems has widely been recognized. In this paper, we propose FPGA architecture with degrading strategy to increasefault-tolerance in a CPU. Previously,duplication and substitution methods have been proposed, but former methodswaste redundant circuits and later methods increase computing speed as faults occur. We propose a re-constitutionmethod with FPGA technology. Using our method, executionspeed of the CPU gradually decreases as permanent faultsoccur.The CPU consists of Functional Blocks FB), that isre-configurable logic blocks. When a fault occures, the broken FB is discarded. As the number of valid FB decreases, function units of it is scaled down, therefore, exection timeincreases. In our simulation, speed degradation is less than100% when 70% of whole FBs are broken.Compared withprevious methods, speed degradation is smaller in case thatmany permanent faults occure.