Digital filter design
Discrete-time signal processing (2nd ed.)
Discrete-time signal processing (2nd ed.)
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Two-Dimensional Digital Filters
Two-Dimensional Digital Filters
Fitting Optimal Piecewise Linear Functions Using Genetic Algorithms
IEEE Transactions on Pattern Analysis and Machine Intelligence
High Performance Computing by Context Switching Reconfigurable Logic
Proceedings of the 16th European Simulation Multiconference on Modelling and Simulation 2002
Evolving an Adaptive Digital Filter
EH '00 Proceedings of the 2nd NASA/DoD workshop on Evolvable Hardware
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
An analysis of the behavior of a class of genetic adaptive systems.
An analysis of the behavior of a class of genetic adaptive systems.
EH '05 Proceedings of the 2005 NASA/DoD Conference on Evolvable Hardware
| Hi-index | 0.00 |
This work presents a hardware implementation of an FIR filter that is self-adaptive; that responds to arbitrary frequency response landscapes; that has built-in coefficient error tolerance capabilities; and that has a minimal adaptation latency. This hardware design is based on a heuristic genetic algorithm. Experimental results show that the proposed design is more efficient than non-evolutionary designs even for arbitrary response filters. As a byproduct, the paper also presents a novel flow for the complete hardware design of what is termed as an Evolutionary System on Chip (ESoC). With the inclusion of an evolutionary process, the ESoC is a new paradigm in modern System on Chip (SoC) designs. The ESoC methodology could be a very useful structured FPGA/ASIC implementation alternative in many practical applications of FIR filters.