An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
| Hi-index | 0.00 |
The objective of this paper is to analyze the detection of defects located in Look-Up-Tables (LUTs) of SRAM-based FPGAs in the context of delay testing. Firstly, the static and dynamic behaviors of FPGA LUTs are described. Secondly, it is demonstrated that physical defects in FPGA LUTs can create delay faults. The detection of such delay faults is analyzed andrequirements on test vectors are derived. Finally, an optimal test sequence detecting all possible delay faults in a LUT is defined in the context of a Manufacturing-Oriented Test Procedure (MOTP) as well as in the context of an Application-Oriented Test Procedure (AOTP).