Automatic Configuration Generation for FPGA Interconnect Testing

Authors:
Mehdi Baradaran Tahoori;Subhasish Mitra
Affiliations:
-;-
Venue:
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Year:
2003

Citing 0
Cited 6

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Abstract

We present a new automatic test configuration generationtechnique for manufacturing testing of interconnect network ofSRAM-based FPGA architectures. The technique guaranteesdetection of open and bridging faults in all wiring channels andprogrammable switches in the interconnects. Only 8 testconfigurations are required to achieve 100% coverage of stuck-open,stuck-closed, open and bridging faults in theinterconnects of Xilinx Virtex FPGAs.