Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Foundations of programming languages
Foundations of programming languages
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Validity Checking for Combinations of Theories with Equality
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CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
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CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
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ASIAN '99 Proceedings of the 5th Asian Computing Science Conference on Advances in Computing Science
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ICCL '98 Proceedings of the 1998 International Conference on Computer Languages
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HLDVT '03 Proceedings of the Eighth IEEE International Workshop on High-Level Design Validation and Test Workshop
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ACM Computing Surveys (CSUR)
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Algebraic verification techniques manipulate the structure of a circuit while preserving its behavior. Algorithmic verification techniques verify properties about the behavior of a circuit. These two techniques have complementary strengths: algebraic techniques are largely independent of the size of the state space, and algorithmic techniques are highly automated. It is desirable to exploit both in the same verification. However, algebraic techniques often use stream-based models of circuits, while algorithmic techniques use state-based models. We prove the consistency of stream- and state-based interpretations of circuit models, and show how stream-based verification results can be used hand-in-hand with state-based verification results. Our approach allows us to combine stream-based algebraic rewriting and state-based reasoning, using SMV and SVC, to verify a pipelined microarchitecture with speculative execution.