Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
A formal proof of absence of deadlock for any acyclic network of PCI buses
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Using “test model-checking” to verify the Runway-PA8000 memory model
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Formal modeling and validation applied to a commercial coherent bus: a case study
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Protocol Verification by Aggregation of Distributed Transactions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
FM-Trends 98 Proceedings of the International Workshop on Current Trends in Applied Formal Method: Applied Formal Methods
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The transaction ordering problem of the original PCI 2.1 standard bus specification violates the desired correctness property of maintaining the so called 'Producer/Consumer' relationship between writers and readers. In [3], a correction to this ordering problem was proposed and informally proved (called the \HP solution" here). In this paper, we present a formalization of the PCI 2.1 protocol in PVS. We formalize the fact that with Local Master ID added to the protocol no completion stealing is possible and the Producer/Consumer property is provided even in the presence of multiple readers. The state of our proofs leading to this result, as well as some of the much needed enhancements to theorem-proving frameworks that will greatly facilitate similar proofs, are also elaborated.