A formal proof of absence of deadlock for any acyclic network of PCI buses
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
Formal Methods in System Design - Special issue on formal methods for computer-added design
Proceedings of the 11th International Conference on Computer Aided Verification
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Routing Information Protocol in HOL/SPIN
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Abstract BDDs: A Technque for Using Abstraction in Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Symbolic Model Checking with Rich ssertional Languages
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Experience with Predicate Abstraction
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Verification of Infinite-State Systems by Combining Abstraction and Reachability Analysis
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Verifying Systems with Replicated Components in Murphi
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Incremental Proof of the Producer/Consumer Property for the PCI Protocol
ZB '02 Proceedings of the 2nd International Conference of B and Z Users on Formal Specification and Development in Z and B
Property Dependent Abstraction of Control Structure for Software Verification
FME '02 Proceedings of the International Symposium of Formal Methods Europe on Formal Methods - Getting IT Right
| Hi-index | 0.00 |
Previously [MHG98,MHJG00], we reported our efforts to verify the producer/consumer transaction ordering property for the PCI 2.1 protocol extended with local master IDs. Although our efforts were met with some success, we were unable to show that all execution traces of all acyclic PCI networks satisfy this transaction ordering property. In this paper, we present a verification technique based on network symmetry classes along with a manuMly derived abstraction that allows us to show, at the bus/bridge level, that all execution traces of all acyclic PCI networks satisfy the transaction ordering property. This now completed case study (modulo the validity of the axioms used to characterized the abstraction) suggests several avenues for further work in combining model-checking (algorithmic methods) and theorem-proving (deductive methods) in judicious ways to solve infinite-state verification problems at the bus/interconnect level. It is a concrete illustration of partitioning concerns where designers can specify bus protocols in an operational semantics (rule-based) style, invent abstractions, and carry out finite-state model-checking while verification experts can establish formal properties of the abstraction.