Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
On compliance test of on-chip bus for SOC
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
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The Wishbone System-on-Chip bus protocol, which is developed by the Silicore Corporation, in connection with its characteristics and complexity, it is verified by the model checking approach. Firstly, the communication model of IP cores is created, and a FSM modeling approach for the model is proposed. Secondly, the non-starvation and fairness properties are specified using the computation tree logic. Finally these properties are verified against the model with the help of the model checking tool SMV. The result shows that there is a bus starvation scenario which will be caused by the unfairness of arbiter. This research demonstrates that there are some flaws with the specification of Wishbone System-on-Chip bus protocol. It also reflects that the arbitration mechanism is prone to flaw and therefore the formal modeling and verification is necessary.