Specification of an Asynchronous On-chip Bus

  • Authors:
  • Juha Plosila;Tiberiu Seceleanu

  • Affiliations:
  • -;-

  • Venue:
  • ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
  • Year:
  • 2002

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Abstract

The latest improvements in the technology of digital devices allow designers to build whole systems on a single silicon chip. New problems arise in this context, one of them being the complexity of interconnections. Optimizing interfaces has become a tedious design step. Other problematic issues are global clock signal distribution and design composability, for which asynchronous design methodology proves to be a good solution. Formal methods can be used to verify the logical correctness of digital hardware. These methods are well-featured for asynchronous designs. This study introduces asynchronous bus modeling aspects in the formal framework of Action Systems.