The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Concurrency and Computation: Practice & Experience - 2002 ACM Java Grande—ISCOPE Conference Part I
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Reasoning about the ARM weakly consistent memory model
Proceedings of the 2008 ACM SIGPLAN workshop on Memory systems performance and correctness: held in conjunction with the Thirteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '08)
Foundations of the C++ concurrency memory model
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
The semantics of power and ARM multiprocessor machine code
Proceedings of the 4th workshop on Declarative aspects of multicore programming
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
JRF-E: using model checking to give advice on eliminating memory model-related bugs
Proceedings of the IEEE/ACM international conference on Automated software engineering
Sound and complete monitoring of sequential consistency for relaxed memory models
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Testing concurrent programs on relaxed memory models
Proceedings of the 2011 International Symposium on Software Testing and Analysis
Litmus tests for comparing memory consistency models: how long do they need to be?
Proceedings of the 48th Design Automation Conference
What's decidable about weak memory models?
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
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Well-defined memory consistency models are necessary for writing correct parallel software Developing and understanding formal specifications of hardware memory models is a challenge due to the subtle differences in allowed reorderings and different specification styles To facilitate exploration of memory model specifications, we have developed a technique for systematically comparing hardware memory models specified using both operational and axiomatic styles Given two specifications, our approach generates all possible multi-threaded programs up to a specified bound, and for each such program, checks if one of the models can lead to an observable behavior not possible in the other model When the models differs, the tool finds a minimal “litmus test” program that demonstrates the difference A number of optimizations reduce the number of programs that need to be examined Our prototype implementation has successfully compared both axiomatic and operational specifications of six different hardware memory models We describe two case studies: (1) development of a non-store atomic variant of an existing memory model, which illustrates the use of the tool while developing a new memory model, and (2) identification of a subtle specification mistake in a recently published axiomatic specification of TSO.