Formal specification of abstract memory models
Proceedings of the 1993 symposium on Research on integrated systems
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
An executable specification, analyzer and verifier for RMO (relaxed memory order)
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
A new solution of Dijkstra's concurrent programming problem
Communications of the ACM
Automated Software Engineering
CIL: Intermediate Language and Tools for Analysis and Transformation of C Programs
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Confirmation of deadlock potentials detected by runtime analysis
Proceedings of the 2006 workshop on Parallel and distributed systems: testing and debugging
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Iterative context bounding for systematic testing of multithreaded programs
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Memory model sensitive bytecode verification
Formal Methods in System Design
Race directed random testing of concurrent programs
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Randomized active atomicity violation detection in concurrent programs
Proceedings of the 16th ACM SIGSOFT International Symposium on Foundations of software engineering
CTrigger: exposing atomicity violation bugs from their hiding places
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
A randomized dynamic program analysis technique for detecting real deadlocks
Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
Multithreaded java program test generation
IBM Systems Journal
On the verification problem for weak memory models
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Communications of the ACM
Adversarial memory for detecting destructive races
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
MemSAT: checking axiomatic specifications of memory models
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 32nd ACM/IEEE International Conference on Software Engineering - Volume 1
Sound and complete monitoring of sequential consistency for relaxed memory models
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Automatic inference of memory fences
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Generating litmus tests for contrasting memory consistency models
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Efficient data race detection for distributed memory parallel programs
Proceedings of 2011 International Conference for High Performance Computing, Networking, Storage and Analysis
Data races vs. data race bugs: telling the difference with portend
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Dynamic synthesis for relaxed memory models
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
Java memory model-aware model checking
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic inference of memory fences
ACM SIGACT News
Parallel assertions for architectures with weak memory models
ATVA'12 Proceedings of the 10th international conference on Automated Technology for Verification and Analysis
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High-performance concurrent libraries, such as lock-free data structures and custom synchronization primitives, are notoriously difficult to write correctly. Such code is often implemented without locks, instead using plain loads and stores and low-level operations like atomic compare-and-swaps and explicit memory fences. Such code must run correctly despite the relaxed memory model of the underlying compiler, virtual machine, and/or hardware. These memory models may reorder the reads and writes issued by a thread, greatly complicating parallel reasoning. We propose Relaxer, a combination of predictive dynamic analysis and software testing, to help programmers write correct, highly-concurrent programs. Our technique works in two phases. First, Relaxer examines a sequentially-consistent run of a program under test and dynamically detects potential data races. These races are used to predict possible violations of sequential consistency under alternate executions on a relaxed memory model. In the second phase, Relaxer re-executes the program with a biased random scheduler and with a conservative simulation of a relaxed memory model in order to create with high probability a predicted sequential consistency violation. These executions can be used to test whether or not a program works as expected when the underlying memory model is not sequentially consistent. We have implemented Relaxer for C and have evaluated it on several synchronization algorithms, concurrent data structures, and parallel applications. Relaxer generates many executions of these benchmarks with violations of sequential consistency, highlighting a number of bugs under relaxed memory models.