Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Graphs & digraphs (2nd ed.)
Correct memory operation of cache-based multiprocessors
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
High-performance computer architecture
High-performance computer architecture
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Principles of concurrent and distributed programming
Principles of concurrent and distributed programming
Paradigm: A Highly Scalable Shared-Memory Multicomputer Architecture
Computer - Special issue on cryptography
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Elements of the Theory of Computation
Elements of the Theory of Computation
Structure of Computers and Computations
Structure of Computers and Computations
Efficient algorithms for verifying memory consistency
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
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Computer architectures supporting shared memory continue to increase in complexity asdesigners seek to improve memory performance. This is especially true of proposals formassively parallel systems with distributed, yet shared, memory. The need to maintain areasonably simple memory model for programmers, in spite of enhancements like cachesand access pipelining, is responsible for many of the complications. We develop a novelgraph model, access graphs, for visualizing processor/memory interaction. Access graphssymbolically represent the causal relationships between load, store, and synchronizationevents. The focus is on two classes of access graphs: pseudo and real. A pseudo accessgraph describes an execution in terms of abstract events familiar to the programmer. Ifthe pseudo access graph is acyclic, then memory consistency is preserved during theexecution. A real access graph describes an execution in terms of physical events knownto the hardware designer. A real access graph must be acyclic since hardware cannotviolate causality. Memory consistency can be verified for a given computer system byproving that for any acyclic real access graph describing a program's execution on thatcomputer, an acyclic pseudo access graph can be derived describing the same execution.