Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Compiler algorithms for synchronization
IEEE Transactions on Computers
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Introduction to algorithms
Compiling programs with user parallelism
Selected papers of the second workshop on Languages and compilers for parallel computing
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Designing memory consistency models for shared-memory multiprocessors
Designing memory consistency models for shared-memory multiprocessors
Optimizing parallel programs with explicit synchronization
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Alpha AXP architecture reference manual (2nd ed.)
Alpha AXP architecture reference manual (2nd ed.)
Parallelism for free: efficient and optimal bitvector analyses for parallel programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Modern compiler implementation in Java
Modern compiler implementation in Java
Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Basic compiler algorithms for parallel programs
Proceedings of the seventh ACM SIGPLAN symposium on Principles and practice of parallel programming
A constant propagation algorithm for explicitly parallel programs
International Journal of Parallel Programming - Special issue on languages and compilers for parallel computing. Part I
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A technique for reducing synchronization overhead in large scale multiprocessors
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture
PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture
Concurrent Programming in Java: Design Principles and Patterns
Concurrent Programming in Java: Design Principles and Patterns
The Java Language Specification
The Java Language Specification
Scalable Shared-Memory Multiprocessing
Scalable Shared-Memory Multiprocessing
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Concurrent SSA Form in the Presence of Mutual Exclusion
ICPP '98 Proceedings of the 1998 International Conference on Parallel Processing
Concurrent Static Single Assignment Form and Constant Propagation for Explicitly Parallel Programs
LCPC '97 Proceedings of the 10th International Workshop on Languages and Compilers for Parallel Computing
Optimizing Parallel SPMD Programs
LCPC '94 Proceedings of the 7th International Workshop on Languages and Compilers for Parallel Computing
Compilation techniques for explicitly parallel programs
Compilation techniques for explicitly parallel programs
Automatic fence insertion for shared memory multiprocessing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
International Journal of Parallel Programming
Lightweight lock-free synchronization methods for multithreading
Proceedings of the 20th annual international conference on Supercomputing
Software Transactional Memory on Relaxed Memory Models
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Incorporation of OpenMP memory consistency into conventional dataflow analysis
IWOMP'08 Proceedings of the 4th international conference on OpenMP in a new era of parallelism
Efficient sequential consistency using conditional fences
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic inference of memory fences
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Stability in weak memory models
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Symmetry-aware predicate abstraction for shared-variable concurrent programs
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Verifying fence elimination optimisations
SAS'11 Proceedings of the 18th international conference on Static analysis
Verification of STM on relaxed memory models
Formal Methods in System Design
Efficient sequential consistency via conflict ordering
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Dynamic synthesis for relaxed memory models
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
Automatic inference of memory fences
ACM SIGACT News
Volition: scalable and precise sequential consistency violation detection
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 27th international ACM conference on International conference on supercomputing
CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency
Journal of the ACM (JACM)
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We present a compiler technique, which is based on Shasha and Snir's delay set analysis, to hide the underlying relaxed memory consistency model for an optimizing compiler for explicitly parallel programs. The compiler presents programmers with a sequentially consistent view of the underlying machine, irrespective of whether it follows a sequentially consistent model or a relaxed model. To hide the underlying relaxed memory consistency model and to guarantee sequential consistency, our algorithm inserts fence instructions by identifying memory-barrier nodes. We reduce the number of fence instructions by exploiting the ordering constraints of the underlying memory consistency model and the property of fence and synchronization operations. We introduce dominators with respect to a node in a control flow graph to identify memory-barrier nodes and show that minimizing the number of memory-barrier nodes is NP-hard