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ACM Transactions on Computer Systems (TOCS)
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reasoning about systems with many processes
Journal of the ACM (JACM)
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SIAM Journal on Computing
The implementation of the Cilk-5 multithreaded language
PLDI '98 Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation
A Unified Formalization of Four Shared-Memory Models
IEEE Transactions on Parallel and Distributed Systems
Model-checking of correctness conditions for concurrent objects
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How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
On the verification problem for weak memory models
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The Art of Multiprocessor Programming
The Art of Multiprocessor Programming
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
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Reasoning about the implementation of concurrency abstractions on x86-TSO
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Sound and complete monitoring of sequential consistency for relaxed memory models
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Partial-coherence abstractions for relaxed memory models
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Deciding robustness against total store ordering
ICALP'11 Proceedings of the 38th international conference on Automata, languages and programming - Volume Part II
Stability in weak memory models
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
A verification-based approach to memory fence insertion in relaxed memory systems
Proceedings of the 18th international SPIN conference on Model checking software
Verifying fence elimination optimisations
SAS'11 Proceedings of the 18th international conference on Static analysis
Counter-Example guided fence insertion under TSO
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic inference of memory fences
ACM SIGACT News
A verification-based approach to memory fence insertion in PSO memory systems
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Partial orders for efficient bounded model checking of concurrent software
CAV'13 Proceedings of the 25th international conference on Computer Aided Verification
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We present algorithms for checking and enforcing robustness of concurrent programs against the Total Store Ordering (TSO) memory model. A program is robust if all its TSO computations correspond to computations under the Sequential Consistency (SC) semantics. We provide a complete characterization of non-robustness in terms of so-called attacks: a restricted form of (harmful) out-of-program-order executions. Then, we show that detecting attacks can be parallelized, and can be solved using state reachability queries under the SC semantics in a suitably instrumented program obtained by a linear size source-to-source translation. Importantly, the construction is valid for an unbounded number of memory addresses and an arbitrary number of parallel threads. It is independent from the data domain and from the size of store buffers in the TSO semantics. In particular, when the data domain is finite and the number of addresses is fixed, we obtain decidability and complexity results for robustness, even for a parametric number of threads. As a second contribution, we provide an algorithm for computing an optimal set of fences that enforce robustness. We consider two criteria of optimality: minimization of program size and maximization of its performance. The algorithms we define are implemented, and we successfully applied them to analyzing and correcting several concurrent algorithms.