The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
An executable specification, analyzer and verifier for RMO (relaxed memory order)
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem
The Power of QDDs (Extended Abstract)
SAS '97 Proceedings of the 4th International Symposium on Static Analysis
Symbolic Verification with Periodic Sets
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
On the verification problem for weak memory models
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Getting rid of store-buffers in TSO analysis
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
A verification-based approach to memory fence insertion in relaxed memory systems
Proceedings of the 18th international SPIN conference on Model checking software
Counter-Example guided fence insertion under TSO
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Towards LTL model checking of unmodified thread-based c & c++ programs
NFM'12 Proceedings of the 4th international conference on NASA Formal Methods
Automatic inference of memory fences
ACM SIGACT News
A verification-based approach to memory fence insertion in PSO memory systems
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
MEMORAX, a precise and sound tool for automatic fence insertion under TSO
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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This paper addresses the problem of verifying programs for the relaxed memory models implemented in modern processors. Specifically, it considers the TSO (Total Store Order) relaxation, which corresponds to the use of store buffers. The proposed approach proceeds by using finite automata to symbolically represent the possible contents of the store buffers. Store, load and commit operations then correspond to operations on these finite automata. The advantage of this approach is that it operates on (potentially infinite) sets of buffer contents, rather than on individual buffer configurations. This provides a way to tame the explosion of the number of possible buffer configurations, while preserving the full generality of the analysis. It is thus possible to check even designs that exploit the relaxed memory model in unusual ways. An experimental implementation has been used to validate the feasibility of the approach.