Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Advances in Petri nets 1986, part I on Petri nets: central models and their properties
Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
Value speculation scheduling for high performance processors
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
ACM Computing Surveys (CSUR)
Handbook of Theoretical Computer Science: Formal Models and Semantics
Handbook of Theoretical Computer Science: Formal Models and Semantics
The Alpha 21264 Microprocessor
IEEE Micro
Memory ordering in modern microprocessors, Part II
Linux Journal
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Spin model checker, the: primer and reference manual
Spin model checker, the: primer and reference manual
The semantics of power and ARM multiprocessor machine code
Proceedings of the 4th workshop on Declarative aspects of multicore programming
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
Systems and Software Verification: Model-Checking Techniques and Tools
Systems and Software Verification: Model-Checking Techniques and Tools
User-Level Implementations of Read-Copy Update
IEEE Transactions on Parallel and Distributed Systems
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Modeling parallel algorithms at the architecture level enables exploring side-effects of the weakly ordered nature of modern processors. Formal verification of such models with model-checking can ensure that algorithm guarantees will hold even in the presence of the most aggressive compiler and processor optimizations. This paper proposes a virtual architecture to model the effects of such optimizations. It first presents the OoOmem framework to model out-of-order memory accesses. It then presents the OoOisched framework to model the effects of out-of-order instruction scheduling. These two frameworks are explained and tested using weaklyordered memory interaction scenarios known to be affected by weak ordering. Then, modeling of user-level RCU (Read- Copy Update) synchronization algorithms is presented. It uses the virtual architecture proposed to verify that the RCU guarantees are indeed respected.