Linearizability: a correctness condition for concurrent objects
ACM Transactions on Programming Languages and Systems (TOPLAS)
Programming DEC-Alpha based multiprocessors the easy way (extended abstract)
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Memory Consistency and Process Coordination for SPARC Multiprocessors
HiPC '00 Proceedings of the 7th International Conference on High Performance Computing
Java: Memory Consistency and Process Coordination
DISC '98 Proceedings of the 12th International Symposium on Distributed Computing
Information-Flow Models for Shared Memory with an Application to the PowerPC Architecture
IEEE Transactions on Parallel and Distributed Systems
Critical Sections and Producer/Consumer Queues in Weak Memory Systems
ISPAN '97 Proceedings of the 1997 International Symposium on Parallel Architectures, Algorithms and Networks
Towards a Formal Model of Shared Memory Consistency for Intel Itanium(tm)
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Tight Bounds for Critical Sections in Processor Consistent Platforms
IEEE Transactions on Parallel and Distributed Systems
Specifying memory consistency of write buffer multiprocessors
ACM Transactions on Computer Systems (TOCS)
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Complete framework for memory consistency with applications to the itanium architecture
Complete framework for memory consistency with applications to the itanium architecture
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A complete framework for modelling memory consistency that includes register and control dependencies is presented. It allows us to determine whether or not a given computation could have arisen from a given program running on a given multiprocessor architecture. The framework is used to provide an exact description of the computations of (a subset of) the Itanium instruction set on an Itanium multiprocessor architecture. We show that capturing register and control dependencies is crucial: a producer/consumer problem is solvable without using strong synchronization primitives on Itanium multiprocessors, but is impossible without exploiting these dependencies.