Algorithms for mutual exclusion
Algorithms for mutual exclusion
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
Memory consistency and process coordination for SPARC v8 multiprocessors (brief announcement)
Proceedings of the nineteenth annual ACM symposium on Principles of distributed computing
Java: Memory Consistency and Process Coordination
DISC '98 Proceedings of the 12th International Symposium on Distributed Computing
Characterizations for Java Memory Behavior
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Limitations and capabilities of weak memory consistency systems
Limitations and capabilities of weak memory consistency systems
Cooperating Sequential Processes, Technical Report EWD-123
Cooperating Sequential Processes, Technical Report EWD-123
A Characterization of Scalable Shared Memories
ICPP '93 Proceedings of the 1993 International Conference on Parallel Processing - Volume 01
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Can out-of-order instruction execution in multiprocessors be made sequentially consistent?
NPC'05 Proceedings of the 2005 IFIP international conference on Network and Parallel Computing
DISC'06 Proceedings of the 20th international conference on Distributed Computing
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Simple and unified non-operational specifications of the three memory consistency models Total Store Ordering (TSO), Partial Store Ordering (PSO), and Relaxed Memory Order (RMO) of SPARC multiprocessors are presented and proved correct. The specifications are intuitive partial order constraints on possible computations and are derived from natural successive weakening of Lamport's Sequential Consistency. The formalisms are then used to determine the capabilities of each model to support solutions to critical section coordination and both set and queue variants of producer/consumer coordination without resorting to expensive synchronization primitives. Our results show that none of RMO, PSO nor TSO is capable of supporting a read/write solution to the critical section problem, but each can support such a solution to some variants of the producer/consumer problem. These results contrast with the two previous attempts to specify these machines, one of whichwould incorrectly imply a read/write solution to the critical section problem for TSO, and the other of which is too complicated to be useful to programmers. Our general framework for defining and proving the correctness of the memory consistency models was key in uncovering the previous error and in achieving our simplification, and hence may be of independent interest.