Experience Using Multiprocessor Systems—A Status Report
ACM Computing Surveys (CSUR)
X-Tree: A tree structured multi-processor computer architecture
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Dynamic Page Migration in Multiprocessors with Distributed Global Memory
IEEE Transactions on Computers
Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
Memory access buffering in multiprocessors
25 years of the international symposia on Computer architecture (selected papers)
VLSI based design principles for MIMD multiprocessor computers with distributed memory management
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
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An experimental multiprocessor computer was designed and built in order to explore the feasibility of certain internal communication mechanisms. The system consisted of seven processing elements, each containing a part of the global memory connected to a local bus. For each processor the global memory is seen as one single, linearly addressable structure. The processing elements were all connected to a common, global bus, consisting of three separate busses in order to increase the capacity. A bus selection unit was designed, capable of making a unique bus selection for each request, within a fraction of a memory cycle. The experiments have shown that communication structures based on distributed global memory and global bus systems can be used efficiently for medium scale systems.