Memory Access Dependencies in Shared-Memory Multiprocessors
IEEE Transactions on Software Engineering
Parallel discrete event simulation
Communications of the ACM - Special issue on simulation
Distributed Shared Memory: A Survey of Issues and Algorithms
Computer - Distributed computing systems: separate resources acting as one
The SPARC architecture manual: version 8
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SPLASH: Stanford parallel applications for shared-memory
ACM SIGARCH Computer Architecture News
The Wisconsin Wind Tunnel: virtual prototyping of parallel computers
SIGMETRICS '93 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems
The accuracy of trace-driven simulations of multiprocessors
SIGMETRICS '93 Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Cost/performance of a parallel computer simulator
PADS '94 Proceedings of the eighth workshop on Parallel and distributed simulation
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
Timepatch: a novel technique for the parallel simulation of multiprocessor caches
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems
A comparative study of conservative and optimistic trace-driven simulations
SS '95 Proceedings of the 28th Annual Simulation Symposium
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We present an execution model for parallel simulation of a distributed shared memory architecture. The model captures the processor-memory interaction and abstracts the memory subsystem. Using this model we show how parallel, on-line, partially-ordered memory traces can be correctly predicted without interacting with the memory subsystem. We also outline a parallel optimistic memory simulator that uses these traces, finds a global order among all events, and returns correct data and timing to each processor. A first evaluation of the amount of concurrency that our model can extract for an ideal multiprocessor shows that processors may execute relatively long instruction sequences without violating the causality constraints. However parallel simulation efficiency is highly dependent on the memory consistency model and the application characteristics.