A model for parallel simulation of distributed shared memory
MASCOTS '96 Proceedings of the 4th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
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We consider the evaluation of the memory hierarchy of multiprocessor systems via parallel trace driven simulation. We study two parallel simulation schemes: a conservative one using an algorithm proposed by Y-B Lin et al. (1992) whose main characteristic is to insert the shared references from every trace in all other traces, and an optimistic one using a Time Warp like algorithm (D. Jefferson, 1985). We compare, qualitatively and quantitatively, the major causes of overhead and the overall performance of the two methods. In addition, we discuss the tradeoffs in terms of implementation and debugging effort and of application to more general architectural simulation. The optimistic scheme is more complex but, in general, has slightly better performance, is more general, and does not require preprocessing.