Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
Verification techniques for cache coherence protocols
ACM Computing Surveys (CSUR)
Memory consistency and event ordering in scalable shared-memory multiprocessors
25 years of the international symposia on Computer architecture (selected papers)
Location Consistency-A New Memory Model and Cache Consistency Protocol
IEEE Transactions on Computers
Cache-Only Memory Architectures
Computer
The Murphi Verification System
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Memory Management for Large-Scale NUMA Multiprocessors
Memory Management for Large-Scale NUMA Multiprocessors
Instruction scheduling for a tiled dataflow architecture
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
The Verification of the On-Chip COMA Cache Coherence Protocol
AMAST 2008 Proceedings of the 12th international conference on Algebraic Methodology and Software Technology
Implementation and evaluation of a microthread architecture
Journal of Systems Architecture: the EUROMICRO Journal
An implementation of the SANE Virtual Processor using POSIX threads
Journal of Systems Architecture: the EUROMICRO Journal
Evaluating CMPs and Their Memory Architecture
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
The implementation of an SVP many-core processor and the evaluation of its memory architecture
ACM SIGARCH Computer Architecture News
Resource-agnostic programming for many-core microgrids
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Heterogeneous integration to simplify many-core architecture simulations
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management
Microprocessors & Microsystems
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This paper describes an on-chip COMA cache coherency protocol to support the microthread model of concurrent program composition. The model gives a sound basis for building multi-core computers as it captures concurrency, abstracts communication and identifies resources, such as processor groups explicitly and where mapping and scheduling is performed dynamically. The result is a model where binary compatibility is guaranteed over arbitrary numbers of cores and where backward binary compatibility is also assured. We present the design of a memory system with relaxed synchronisation and consistency constraints that matches the characteristics of this model. We exploit an on-chip COMA organisation, which provides a flexible and transparent partitioning between processors and memory. This paper describes the coherency protocol and consistency model and describes work undertaken on the validation of the model and the development of a co-simulator to the Microgrid CMP emulator.