Location Consistency-A New Memory Model and Cache Consistency Protocol
IEEE Transactions on Computers
Technology Independent Area and Delay Estimations for MicroprocessorBuilding Blocks
Technology Independent Area and Delay Estimations for MicroprocessorBuilding Blocks
POWER5 System microarchitecture
IBM Journal of Research and Development - POWER5 and packaging
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
A case for chip multiprocessors based on the data-driven multithreading model
International Journal of Parallel Programming
Scheduling FFT computation on SMP and multicore systems
Proceedings of the 21st annual international conference on Supercomputing
On-chip COMA cache-coherence protocol for microgrids of microthreaded cores
Euro-Par'07 Proceedings of the 2007 conference on Parallel processing
µTC: an intermediate language for programming chip multiprocessors
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Evaluating CMPs and Their Memory Architecture
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
The implementation of an SVP many-core processor and the evaluation of its memory architecture
ACM SIGARCH Computer Architecture News
Journal of Systems Architecture: the EUROMICRO Journal
Resource-agnostic programming for many-core microgrids
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Concurrent non-deferred reference counting on the Microgrid: first experiences
IFL'10 Proceedings of the 22nd international conference on Implementation and application of functional languages
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Heterogeneous integration to simplify many-core architecture simulations
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
A polyphase filter for GPUs and multi-core processors
Proceedings of the 2012 workshop on High-Performance Computing for Astronomy Date
CEFP'11 Proceedings of the 4th Summer School conference on Central European Functional Programming School
ARCS'13 Proceedings of the 26th international conference on Architecture of Computing Systems
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management
Microprocessors & Microsystems
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Future many-core processor systems require scalable solutions that conventional architectures currently do not provide. This paper presents a novel architecture that demonstrates the required scalability. It is based on a model of computation developed in the AETHER project to provide a safe and composable approach to concurrent programming. The model supports a dynamic approach to concurrency that enables self-adaptivity in any environment so the model is quite general. It is implemented here in the instruction set of a dynamically scheduled RISC processor and many such processors form a microgrid. Binary compatibility over arbitrary clusters of such processors and an inherent scalability in both area and performance with concurrency exploited make this a very promising development for the era of many-core chips. This paper introduces the model, the processor and chip architecture and its emulation on a range of computational kernels. It also estimates the area of the structures required to support this model in silicon.