Technology Independent Area and Delay Estimations for MicroprocessorBuilding Blocks

Authors:
Shashank Gupta;Steven W. Keckler;Doug Burger
Affiliations:
-;-;-
Venue:
Technology Independent Area and Delay Estimations for MicroprocessorBuilding Blocks
Year:
2001

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Abstract

As technologies continue to shrink and sizes of chips continue to get larger, the transistor budget available for design is growing rapidly. Accurate area and delay estimates for the various structures would help in estimating the approximate area and delay estimates for blocks which could be used to make preliminary analysis of new designs. In this work, we identify some of the basic architecture building blocks and provide area and delay estimates for them. Published die photos of various processors were analyzed to make area estimates which were converted to technology independent units considering the process parameters used for the chip fabrication. Using those estimates, a number of design configurations have been analyzed and projections about the area and delay of future designs are made.