Transputer reference manual
Integrating polling, interrupts, and thread management
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Hardware scheduling support in SMP architectures
Proceedings of the conference on Design, automation and test in Europe
Implementation and evaluation of a microthread architecture
Journal of Systems Architecture: the EUROMICRO Journal
Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Task management in MPSoCs: an ASIP approach
Proceedings of the 2009 International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
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System-on-chip integrate an increasing amount of processing elements and on-chip communication is of particular importance. Rising communication rates with varying delays require efficient techniques to signal events related to the on-chip communication to the application software. While latencies are commonly hidden by multithreading, the signaling of events is usually done by polling or interrupts. With rising rates of such events the classic techniques expose an increasing software overhead that becomes significantly important. In this paper we present the concept of hardware-based operating system queue manipulation (HW-OSQM) to offload the process of event signaling. The concept is implemented as a flexible hardware accelerator which integrates with the communication hardware and autonomously manipulates the queue data structures of the operating system. It eliminates the associated software overhead and utilizes small additional resources while allowing for the required flexibility. The performance improvement shows that HW-OSQM can nearly eliminate any overhead in software.