Single Assignment C: efficient support for high-level array operations in a functional setting
Journal of Functional Programming
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
Implementation and evaluation of a microthread architecture
Journal of Systems Architecture: the EUROMICRO Journal
Strategies for compiling µTC to novel chip Multiprocessors
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
On-chip COMA cache-coherence protocol for microgrids of microthreaded cores
Euro-Par'07 Proceedings of the 2007 conference on Parallel processing
µTC: an intermediate language for programming chip multiprocessors
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
A polyphase filter for GPUs and multi-core processors
Proceedings of the 2012 workshop on High-Performance Computing for Astronomy Date
Fine grained parallelism in recursive function calls
PPAM'11 Proceedings of the 9th international conference on Parallel Processing and Applied Mathematics - Volume Part II
Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management
Microprocessors & Microsystems
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Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of silicon technology. This paper presents a many-core processor that supports an abstract model of concurrency, based on a Self-adaptive Virtual Processor (SVP). This processor implements instructions, which automatically map and schedule threads providing a code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this processor architecture is the memory system. This paper briefly presents the model and evaluates its memory architecture.