Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
On the OBDD-Representation of General Boolean Functions
IEEE Transactions on Computers
Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
New techniques for efficient verification with implicitly conjoined BDDs
DAC '94 Proceedings of the 31st annual Design Automation Conference
High performance BDD package by exploiting memory hierarchy
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Implementation of an efficient parallel BDD package
DAC '96 Proceedings of the 33rd annual Design Automation Conference
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
A new scheme for memory-efficient probabilistic verification
IFIP TC6/ 6.1 international conference on formal description techniques IX/protocol specification, testing and verification XVI on Formal description techniques IX : theory, application and tools: theory, application and tools
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
An Analysis of Bitstate Hashing
Formal Methods in System Design
Binary decision diagrams on network of workstation
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Improved probabilistic verification by hash compaction
CHARME '95 Proceedings of the IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Using Magnatic Disk Instead of Main Memory in the Murphi Verifier
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Reliable Hashing without Collosion Detection
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Parallelizing the Murphi Verifier
CAV '97 Proceedings of the 9th International Conference on Computer Aided Verification
Better Verification Through Symmetry
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Exploiting Transition Locality in the Disk Based Mur phi Verifier
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Dynamic Delayed Duplicate Detection for External Memory Model Checking
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Layered Duplicate Detection in External-Memory Model Checking
SPIN '08 Proceedings of the 15th international workshop on Model Checking Software
Hierarchical Adaptive State Space Caching Based on Level Sampling
TACAS '09 Proceedings of the 15th International Conference on Tools and Algorithms for the Construction and Analysis of Systems: Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2009,
Search-order independent state caching
Transactions on Petri nets and other models of concurrency IV
Exploiting hub states in automatic verification
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
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In this paper we present an algorithm to contrast state explosion when using Explicit State Space Exploration to verify protocols. We show experimentally that protocols exhibit transition locality. We present a verification algorithm that exploits transition locality as well as an implementation of it within the Murϕ verifier. Our algorithm is compatible with all Breadth First (BF) optimization techniques present in the Murϕ verifier and it is by no means a substitute for any of them. In fact, since our algorithm trades space with time, it is typically most useful when one runs out of memory and has already used all other state reduction techniques present in the Murϕ verifier. Our experimental results show that using our approach we can typically save more than 40% of RAM with an average time penalty of about 50% when using (Murϕ) bit compression and 100% when using bit compression and hash compaction.