Diagnostic modelling of digital systems with multi-level decision diagrams
MS'06 Proceedings of the 17th IASTED international conference on Modelling and simulation
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A method is proposed for combinational deterministic test pattern generation using a uniform functional fault model for combinational circuits. This includes an approach, which allows to find the types of faults that may occur in a real circuit and to determine their probabilities. Additionally, a defect-oriented deterministic test generation tool was developed (DOT), and the experimental data obtained by the tool for ISCASý85 benchmarks are presented. It was shown that 100% stuck-at fault tests covered only about80-90% physical defects. The main feature of the new tool is its ability to reach 100% defect efficiency for the given set of defects by proving the redundancy of not detected defects. An interesting conclusion of the experiments is also that up to 25 % of the defects cannot be covered by any voltage test approaches.