Exact evaluation of diagnostic test resolution
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On improving fault diagnosis for synchronous sequential circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Fault dictionary compression and equivalence class computation for sequential circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Diagnostic Fault Simulation of Sequential Circuits
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A Diagnostic Fault Simulator for Fast Diagnosis of Bridge Faults
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
Diagnostic fault simulation for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
Journal of Electronic Testing: Theory and Applications
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This article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices, and for large circuits is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits with known deterministic tests. The diagnostic fault simulator has also been modified to diagnose defects, given the output responses of failing devices. Results on simulated bridging defects show that the diagnosis time is comparable to the time for fault simulation with fault dropping.