Automatic Verification of Sequential Circuits Using Temporal Logic
IEEE Transactions on Computers
Approaches to multi-level sequential logic synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new method for verifying sequential circuits
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
On the temporal equivalence of sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Finite state machine verification on MIMD machines
EURO-DAC '92 Proceedings of the conference on European design automation
Verification of asynchronous interface circuits with bounded wire delays
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
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The problem of verifying the equivalence of interacting finite state machines (FSMs) described at the logic level is addressed. The problem is formulated as that of checking for the equivalence of the reset/starting states of the two FSMs. First, separate sum-of-product representations of the ON-sets and OFF-sets of each of the flip-flop inputs and primary outputs of the sequential circuit, are extracted using the PODEM algorithm. We describe a fast algorithm for state differentiation based on this representation. The input as well as the state space is implicitly enumerated through a process of repeated cube intersections to generate the State Transition Graph (STG).In contrast to previous approaches, this algorithm can be efficiently generalized for verifying distributed-style specifications of interacting sequential circuits, exploiting the nature of the interconnection topology. Pipeline latches in a distributed-style specification typically do not add complexity to the sequential behavior of a circuit, but greatly add to the complexity of traditional approaches to verifying sequential circuits. Pipeline latches are easily incorporated into our generalized, hierarchical verification strategy whereby the states of pipeline latches can be implicitly enumerated.Experimental results indicate the superior efficiency of this approach as compared to previous approaches for FSM verification. It is possible to verify examples with more than 1050 states.