Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
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The generation of a universal test set (UTS) for unate functions is used as a starting point. This test set is complete and minimal for the set of all unateness-preserving faults. However, for functions that are not unate in any variable, the UTS generated by this algorithm is the exhaustive set. An algorithm is presented that computes a good functional test set (GFTS) of reasonable size even for such functions. The algorithm does this by breaking up functions into more unate components, recursively computing GFTS for them, and combining the test sets in an appropriate way. The GFTS generated by the algorithm is compared to random test sets of the same size for gate-level fault coverage in typical implementations.