Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Logic synthesis for efficient pseudoexhaustive testability
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
PLATO: a CAD tool for logic synthesis based on decomposition
EURO-DAC '91 Proceedings of the conference on European design automation
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A procedure for designing combinational circuits suitable for built-in verification testing is presented. Unlike the traditional approach, where the design of a test pattern generator follows the functional logic synthesis, in our method the built-in self-test synthesis tightly interacts with the functional logic design. The experimental results indicate that a significant reduction in testing time at a negligible area/performance penalty can be obtained in the circuits designed using the proposed verification testing oriented logic synthesis procedure.