A note on designing logical circuits using SAT

  • Authors:
  • Giovani Gomez Estrada

  • Affiliations:
  • Max-Planck-Institute, Stuttgart, Germany

  • Venue:
  • ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
  • Year:
  • 2003

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Abstract

We present a systematic procedure to synthesise and minimise digital circuits using propositional satisfiability. After encoding the truth table into a canonical sum of at most k different products, we seek its minimal satisfiable representation. We show how to use an interesting local search landscape for this minimisation. This approach can be very useful since we can generate exact minimal solutions within reasonably computational resources.