Verification of large synthesized designs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Solution of parallel language equations for logic synthesis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Simplification of non-deterministic multi-valued networks
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SAT-Based Complete Don't-Care Computation for Network Optimization
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IBERAMIA-SBIA'06 Proceedings of the 2nd international joint conference, and Proceedings of the 10th Ibero-American Conference on AI 18th Brazilian conference on Advances in Artificial Intelligence
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Both non-determinism and multi-level networks compactlycharacterize the flexibility allowed in implementing a circuit.A theory for representing and manipulating non-deterministic(ND) multi-level networks is developed. The theory supports allthe network manipulations commonly applied to deterministicbinary networks, such as node minimization, elimination, anddecomposition. It is shown that an ND network's behavior can beinterpreted in three ways, all of which coincide when the networkis deterministic. Operations performed on an ND network areanalyzed under each interpretation for changes in a network'sbehavior. Modifications of a few operations are given which mustbe used to guarantee that a network's behavior does not violateits external specification. These modifications depend on whichbehavior is being used and the location of related non-determinism.This theory has been implemented in a system,MVSIS. We provide comparisons among the uses of the various behaviors.