Utilizing logic information in multi-level timing simulation

Graph-Based Algorithms for Boolean Function Manipulation

IEEE Transactions on Computers

Dynamic multi-level simulation of digital hardware designs

Simulation

Models and algorithms for race analysis in asynchronous circuits

Models and algorithms for race analysis in asynchronous circuits

Test pattern generation for sequential MOS circuits by symbolic fault simulation

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference

Asynchronous Sequential Switching Circuit

Asynchronous Sequential Switching Circuit

Logic Minimization Algorithms for VLSI Synthesis

Logic Minimization Algorithms for VLSI Synthesis

Statistical timing verification and delay fault detection by formal signal interaction modeling in a multi-level timing simulator

Statistical timing verification and delay fault detection by formal signal interaction modeling in a multi-level timing simulator

Elements of discrete mathematics (McGraw-Hill computer science series)

Elements of discrete mathematics (McGraw-Hill computer science series)