Processor allocation in an N-cube multiprocessor using gray codes
IEEE Transactions on Computers
IEEE Transactions on Computers
Subcube Allocation and Task Migration in Hypercube Multiprocessors
IEEE Transactions on Computers
Subcube Allocation in Hypercube Computers
IEEE Transactions on Computers
Dynamic processor allocation in hypercube computers
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A Top-Down Processor Allocation Scheme for Hypercube Computers
IEEE Transactions on Parallel and Distributed Systems
Augmented Binary Hypercube: A New Architecture for Processor Management
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Performance characteristics of gang scheduling in multiprogrammed environments
SC '97 Proceedings of the 1997 ACM/IEEE conference on Supercomputing
Subcube Fault Tolerance in Hypercube Multiprocessors
IEEE Transactions on Computers
| Hi-index | 0.01 |
The authors propose a new approach for subcube and noncubic processor allocations forhypercube multiprocessors. The main idea is to represent available processors in thesystem by means of a prime cube graph (PC-graph). The PC-graph maintains theinter-relationships between free subcubes and hence reduces both internal and externalprocessor fragmentations. Their simulation results show that the PC-graph approachoutperforms the existing allocation strategies by 25% to 50% under certain loadconditions.