Processor allocation in an N-cube multiprocessor using gray codes
IEEE Transactions on Computers
Subcube Allocation in Hypercube Computers
IEEE Transactions on Computers
A Fast Recognition-Complete Processor Allocation Strategy for Hypercube Computers
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
A New Graph Approach to Minimizing Processor Fragmentation in Hypercube Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
| Hi-index | 14.98 |
Augmented Binary Hypercube (AH) architecture consists of the binary hypercube processor nodes (PNs) and a hierarchy of management nodes (MNs). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs onto PNs, define and prove infeasibility of ideal mappings. We propose easily implementable non-optimal mappings, having negligible overheads on performance. Extensive simulation studies and performance analysis conclude that these algorithms realize significantly better average job completion time and higher processor utilization, as compared to the best sequential allocation schemes and parallel implementation of Free List [7]. AH algorithms can be tuned or adapt to the job and system characteristics, and resource management traffic.