A general purpose multiple way partitioning algorithm
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
On non-linear lower bounds in computational complexity
STOC '75 Proceedings of seventh annual ACM symposium on Theory of computing
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
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A block-oriented programmable design with switching network interconnect is proposed for fast turn-amund, low manufacturing cost, and layout-independent high-speed systems. We introduce the architecture and investigate the constraints and properties originated from the architecture. We show that routability is the most crucial concern for a successful design, and propose objective functions as well as algorithms for switching network optimization. The mapping for the circuits is performed by partitioning, placement, and routing using a maximum matching method. The integration of the whole system domonstrates excellent results in terms of circuit usage.